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 FACULTY of SCIENCE / DEPARTMENT of STATISTICS and COMPUTER SCIENCES Course Catalog http://www.ktu.edu.tr/isbb Phone: +90 0462 +90 (462) 3773112 FENF
FACULTY of SCIENCE / DEPARTMENT of STATISTICS and COMPUTER SCIENCES /

 IST2012 Logical Design 2+0+0 ECTS:4 Year / Semester Spring Semester Level of Course First Cycle Status Compulsory Department DEPARTMENT of STATISTICS and COMPUTER SCIENCES Prerequisites and co-requisites None Mode of Delivery Face to face Contact Hours 14 weeks - 2 hours of lectures per week Lecturer Dr. Öğr. Üyesi Halil İbrahim ŞAHİN Co-Lecturer None Language of instruction Turkish Professional practise ( internship ) None The aim of the course: Understand binary numbers and boole algebra that use in digital systems, learn the logical gates and simplification rules, understand the combinational and sequential logic
 Learning Outcomes CTPO TOA Upon successful completion of the course, the students will be able to : LO - 1 : learn basic boolean rules 4,7,9 1,3,4 LO - 2 : learn basic logical gates 4,5,7,9 1,3,4 LO - 3 : learn simplification of boolen circuits by using boolean rules and teorems 4,5,7 1,3,4 LO - 4 : learn circuits that remember its past and how to use it in computer circuits 4,5,7,9 1,3,4 CTPO : Contribution to programme outcomes, TOA :Type of assessment (1: written exam, 2: Oral exam, 3: Homework assignment, 4: Laboratory exercise/exam, 5: Seminar / presentation, 6: Term paper), LO : Learning Outcome
 Contents of the Course
 Digital Systems and Binary Numbers,Boole Algebra and Logic Gates,Gate-Level Minimization,Combinational Logic,Sequential Logic
 Course Syllabus Week Subject Related Notes / Files Week 1 Number systems and coding Week 2 Number systems and coding Week 3 Binary Arithmetic and logic Week 4 Logic icons, Boolean functions Week 5 Logic icons, Boolean functions Week 6 Simplification of Boolean Functions Week 7 Elements and Circuits of Boole: AND, OR, NOT, Trigger, Register, Shifter, Counter Week 8 Mid-term exam Week 9 Elements and Circuits of Boole: AND,OR, NOT, Trigger, Register, Shifter, Counter Week 10 Designing logic circuits: Adder design, multiplexer design, code converter design Week 11 Designing logic circuits: Adder design, multiplexer design, code converter design Week 12 Short exam Week 13 Designing logic circuits: Adder design, multiplexer design, code converter design Week 14 Arithmetic-logic algorithms and design. Week 15 Arithmetic-logic algorithms and design Week 16 End-of-term exam
 Textbook / Material
 1 Mano, Moris, 2002; Sayısal Tasarım, Literatür Yayıncılık,İstanbul