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| COM 245 | Digital Design | 4+0+0 | ECTS:4 | | Year / Semester | Fall Semester | | Level of Course | First Cycle | | Status | Compulsory | | Department | DEPARTMENT of COMPUTER ENGINEERING | | Prerequisites and co-requisites | None | | Mode of Delivery | Face to face | | Contact Hours | 14 weeks - 4 hours of lectures per week | | Lecturer | -- | | Co-Lecturer | None | | Language of instruction | | | Professional practise ( internship ) | None | | | | The aim of the course: | | This course intends to teach firstly the special problems encountered in the analysis and design of asynchronous sequential networks. Then it is learned that the basic electronic circuits in each IC digital logic family and analyzes their electrical operation. Finally, to understand the theory of operation and circuit limitations of several types of DACs (Digital Analog Converter) and ADCs (Analog Digital Converter) . |
| Learning Outcomes | CTPO | TOA | | Upon successful completion of the course, the students will be able to : | | | | LO - 1 : | achieve analysis and design procedures for the pulse-mode and the fundemental mode asynchronous networks | 1,2,3,4,5,8 | 1 | | LO - 2 : | achive the problems such as races and risks on the fundemental mode asynchronous networks | 1,2,3,8 | 1 | | LO - 3 : | design counters, clocked sequential networks-detectors, and similar networks using flip-flops | 1,3,5,8,11 | 1 | | LO - 4 : | understand the theory of operation and circuit limitations of several types of DACs (Digital Analog Converter) and ADCs (Analog Digital Converter). | 3,4,10 | 1 | | LO - 5 : | construct simple synchronous sequential network based on ROM and PLD devices | 1,2,3,5,8,10 | 1 | | CTPO : Contribution to programme outcomes, TOA :Type of assessment (1: written exam, 2: Oral exam, 3: Homework assignment, 4: Laboratory exercise/exam, 5: Seminar / presentation, 6: Term paper), LO : Learning Outcome | | |
| Discrete and Integrated Circuit Logic Design; Multiple-Output Networks; Flip-Flops, Counters and similar networks, Analysis of clocked sequential networks; Derivation of state graphs and tables; Reduction of state tables state assignment; MSI integrated circuits in sequential network design; Sequential network design with programmable logic devices; State machine design with SM charts; Analysis and synthesis pulse-mode asynchronous circuits; Analysis of fundemental-mode asynchronous sequential networks; Derivation and reduction of primitive tables; State assignment realization of flow tables; Hazards, Asynchronous sequential network design; Interface with analog world. |
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| Course Syllabus | | Week | Subject | Related Notes / Files | | Week 1 | Discrete and Integrated Circuit Logic Design | | | Week 2 | Flip-Flops, Counters and similar sequential networks | | | Week 3 | Analysis of Clocked Sequential networks | | | Week 4 | Derivation of sate graphs and tables | | | Week 5 | Reduction od state tables state assignment | | | Week 6 | MSI Integrated circuits in sequentai network design | | | Week 7 | Sequential Network Design with programmable logic devices | | | Week 8 | State Machine design with SM charts | | | Week 9 | Midterm Exam | | | Week 10 | Analysis and synthesis pulse-mode asynchronous circuits | | | Week 11 | Analysis of fundamental-mode asynchronous sequential networks | | | Week 12 | Derivation and reduction of primitive tables | | | Week 13 | State assigment realization of flow tables | | | Week 14 | Hazards | | | Week 15 | Interface with analog world | | | Week 16 | Final Exam | | | |
| 1 | Fundamentals of logic Design, Fourth Edition, Charles H. Roth., Jr, West publishing company | | | |
| 1 | Digital Design M. Morris Mono, Prentice Hall | | | 2 | Digital Logic Circuit Analysis and Design, V.P. Nelson, H.T. Nagle, J.D. Irwin, Prentice Hall | | | 3 | Digital Systems Principles and Applications, Ronald Torci, Prentice Hall. | | | |
| Method of Assessment | | Type of assessment | Week No | Date | Duration (hours) | Weight (%) | | Mid-term exam | 9 | 12/11/2013 | 2 | 50 | | End-of-term exam | 16 | 7/01/2014 | | 50 | | |
| Student Work Load and its Distribution | | Type of work | Duration (hours pw) | No of weeks / Number of activity | Hours in total per term | | Yüz yüze eğitim | 4 | 14 | 56 | | Sınıf dışı çalışma | 4 | 14 | 56 | | Arasınav için hazırlık | 6 | 1 | 6 | | Arasınav | 2 | 1 | 2 | | Dönem sonu sınavı için hazırlık | 8 | 1 | 8 | | Dönem sonu sınavı | 2 | 1 | 2 | | Total work load | | | 130 |
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