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| BIL3017 | Hardware Description Languages | 3+0+0 | ECTS:4 | | Year / Semester | Fall Semester | | Level of Course | First Cycle | | Status | Elective | | Department | DEPARTMENT of COMPUTER ENGINEERING | | Prerequisites and co-requisites | None | | Mode of Delivery | Face to face, Group study | | Contact Hours | 14 weeks - 3 hours of lectures per week | | Lecturer | -- | | Co-Lecturer | | | Language of instruction | Turkish | | Professional practise ( internship ) | None | | | | The aim of the course: | | The objectives of course are (a) to cover basics of a hardware description language (VHDL) (b) to obtain the ability of designing Finite State Machines (FSMs) (c) to learn how to design basic hardware modules such as register, counter and etc. (d) to use an FPGA board. |
| Learning Outcomes | CTPO | TOA | | Upon successful completion of the course, the students will be able to : | | | | LO - 1 : | Learn embedded systems basics | 2,3,4,12 | | | LO - 2 : | Learn a hardware description laguage (HDL) | 2,3,4,12 | | | LO - 3 : | Design and develope hardware modules with the HDL | 2,3,4,12 | | | LO - 4 : | Perform computer based simulation and applies to real hardware | 2,3,4,12 | | | CTPO : Contribution to programme outcomes, TOA :Type of assessment (1: written exam, 2: Oral exam, 3: Homework assignment, 4: Laboratory exercise/exam, 5: Seminar / presentation, 6: Term paper), LO : Learning Outcome | | |
| Embedded design concepts. Basic structure of a hardware description language. Designing and implementing combinational and sequential circuits in VHDL hardware description language. |
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| Course Syllabus | | Week | Subject | Related Notes / Files | | Week 1 | Introduction, definitions and concepts
| | | Week 2 | Concept of the VHDL hardware description language
| | | Week 3 | Combinational circuit design in VHDL
| | | Week 4 | 1-bit and 4-bit Full adder design
| | | Week 5 | Testing and debugging VHDL code
| | | Week 6 | Introduction to sequential designs
| | | Week 7 | VHDL code for counters
| | | Week 8 | Introduction to Finite state Machines (FSMs)
| | | Week 9 | Midterm exam
| | | Week 10 | Designing Moore and Mealy type FSMs
| | | Week 11 | Extending VHDL designs with components
| | | Week 12 | Programming and testing Spartan FPGA board with Full adder circuit
| | | Week 13 | Programming and testing Spartan FPGA board with counter design
| | | Week 14 | Final Exam | | | Week 15 | Final Exam | | | |
| 1 | Zwolinski, Mark, Digital system design with VHDL, Prentice Hall, 2003: 2nd ed. | | | |
| 1 | Perry, Douglas L. , VHDL: programming by example, McGraw-Hill, 2002 : 4th ed. | | | |
| Method of Assessment | | Type of assessment | Week No | Date | Duration (hours) | Weight (%) | | Mid-term exam | 9 | | 120 | 25 | | Quiz | 6 | | 15 | 10 | | Project | 12 | | | 15 | | End-of-term exam | 15 | | 120 | 50 | | |
| Student Work Load and its Distribution | | Type of work | Duration (hours pw) | No of weeks / Number of activity | Hours in total per term | | Yüz yüze eğitim | 3 | 14 | 42 | | Sınıf dışı çalışma | 2 | 9 | 18 | | Arasınav | 2 | 1 | 2 | | Uygulama | 1 | 3 | 3 | | Proje | 2 | 12 | 24 | | Dönem sonu sınavı | 2 | 14 | 28 | | Total work load | | | 117 |
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