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| ELK1008 | Digital Design | 3+0+1 | ECTS:5 | | Year / Semester | Spring Semester | | Level of Course | First Cycle | | Status | Compulsory | | Department | DEPARTMENT of ELECTRICAL and ELECTRONICS ENGINEERING | | Prerequisites and co-requisites | DC must have been achieved from ELK1013-Introduction To Computer or DC must have been achieved from ELK1007-Introduction To Computer | | Mode of Delivery | Face to face, Lab work | | Contact Hours | 14 weeks - 3 hours of lectures and 1 hour of laboratory per week | | Lecturer | Prof. Dr. Salim KAHVECİ | | Co-Lecturer | ASSOC. PROF. DR. Önder AYDEMİR, | | Language of instruction | Turkish | | Professional practise ( internship ) | None | | | | The aim of the course: | | Understand what's under the hood of a computer.
Learn the principles of digital design.
Learn to systematically debug increasingly complex designs. |
| Learning Outcomes | CTPO | TOA | | Upon successful completion of the course, the students will be able to : | | | | LO - 1 : | understand the fundamental Boolean principles and manipulation and their application to digital desi | 1,2,3,5,6,11 | 1,4 | | LO - 2 : | understand of combinational and sequential digital/logic circuits, and modular design techniques.
| 1,3,5,8,11 | 1 | | LO - 3 : | Understand how to a computer works.
| 1,3,5,8,11,13 | 1 | | LO - 4 : | understand Digital Design methods | 1,3,5,11,13 | 1 | | LO - 5 : | Know how to a hardware programmed to be used for specific purpose. | 1,2,3,8,11,13 | 1 | | CTPO : Contribution to programme outcomes, TOA :Type of assessment (1: written exam, 2: Oral exam, 3: Homework assignment, 4: Laboratory exercise/exam, 5: Seminar / presentation, 6: Term paper), LO : Learning Outcome | | |
| Number systems, decimal numbers, binary numbers, powers of two, number conversions, hexadecimal numbers, bit, byte, nibble,.Adding binary numbers, signed binary numbers, complement of two. Logic gates, logic levels, noise. Logic gates familiy (TTL, CMOS, LVTTL, LVCMOS). Boolean equations, product of sums (POS), sum of products (SOP). Boolean algebra, boolean axioms, Simplifying boolean equations. DeMorgan theorem. Rules for circuit schematics. Multiple output circuits. Priority circuits Dont cares. Tristate buses. Karnough maps. Multiplexers and decoders. Types of delay. Critical paths. Glitch. Introduction to sequential circuits. Bistable circuit, SR, D latch and D flip-flop. Enabled flip flops. Resettable flip-flops. Settable flip-flops. Sequential logic. Synchronous sequential logic design.. Finite state machines (FSM). Moore vs Mealy FSM. Timing, input and output timing constraints. Setup and hold timing constraints. Timing analysis. Clock skew. Meta stablity. Synchronisers. Spatial and temporal paralellism. Hardware description languagesi (HDL). Simulation and synthesis. Systemverilog, HDL simulation. Design of adder, subtracter, comparator and ALU. Shifter, multiplier, divider. Fixed point and signed fixed point numbers. Floating point numbers. Counters, shift registers, arrays of memory, ROM, RAM, DRAM, SRAM. Designing circuits using memory. PLA and FPGA. |
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| Course Syllabus | | Week | Subject | Related Notes / Files | | Week 1 | Introduction to computer architecture. Managing complexity and the digital abstraction. Number systems. | | | Week 2 | Logic gates and logic levels. | | | Week 3 | CMOS transistors. Power consumption. | | | Week 4 | Combinational logic design. Boolean equations. Boolean algebra. | | | Week 5 | From logic to gates. Multilevel combinational logic. Karnaugh maps. | | | Week 6 | Karnaugh maps. Multiplexers and decoders. Timing. Introduction to sequential logic design. | | | Week 7 | Flip-flops and latches. | | | Week 8 | Arithmetic circuits. Number systems. | | | Week 9 | Midterm exam | | | Week 10 | Finite state machines. Timing of sequential logic. | | | Week 11 | Timing of sequential logic. Parallelism. | | | Week 12 | Hardware description languages. Combinational logic. Structural modeling. Sequential logic. | | | Week 13 | More combinational logic. Finite state machines. Parameterized modules. Testbenches. Arithmetic circuits. | | | Week 14 | Synchronous logic design. Finite state machines. | | | Week 15 | ASynchronous logic design. | | | Week 16 | End-of-term exam | | | |
| 1 | Harris D. ve Harris S., 2012; Digital Design and Computer Architecture, Morgan Kaufmann | | | |
| 1 | Nelson P. V., Agle H.T., Carroll D B., Irwin J. D., 1995; Digital Logic Circuit Analysis and Design, Prentice Hall, New Jersey | | | 2 | Arsan T. ve Çölkesen R., Lojik Devre Tasarımı, 2007; Papatya yayıncılık | | | 3 | Altan C. Basılmamış ders notları | | | |
| Method of Assessment | | Type of assessment | Week No | Date | Duration (hours) | Weight (%) | | Mid-term exam | 9 | | 2 | 30 | | Practice | 4
14 | | | 20 | | End-of-term exam | 16 | | 2 | 50 | | |
| Student Work Load and its Distribution | | Type of work | Duration (hours pw) | No of weeks / Number of activity | Hours in total per term | | Yüz yüze eğitim | 3 | 13 | 39 | | Sınıf dışı çalışma | 3 | 12 | 36 | | Laboratuar çalışması | 1 | 5 | 5 | | Arasınav için hazırlık | 5 | 8 | 40 | | Arasınav | 2 | 1 | 2 | | Uygulama | 0 | 0 | 0 | | Klinik Uygulama | 0 | 0 | 0 | | Ödev | 0 | 0 | 0 | | Proje | 0 | 0 | 0 | | Kısa sınav | 0 | 0 | 0 | | Dönem sonu sınavı için hazırlık | 5 | 5 | 25 | | Dönem sonu sınavı | 2 | 1 | 2 | | Diğer 1 | 0 | 0 | 0 | | Diğer 2 | 0 | 0 | 0 | | Total work load | | | 149 |
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