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| EHM3001 | Digital Design | 3+0+0 | ECTS:5 | | Year / Semester | Fall Semester | | Level of Course | First Cycle | | Status | Compulsory | | Department | DEPARTMENT of ELECTRONICS and COMMUNICATION ENGINEERING | | Prerequisites and co-requisites | None | | Mode of Delivery | | | Contact Hours | 14 weeks - 3 hours of lectures per week | | Lecturer | Dr. Öğr. Üyesi Erhan SESLİ | | Co-Lecturer | Assistant Prof. Dr. Emin Tugcu, Assistant Prof. Dr. Cenk Albayrak | | Language of instruction | Turkish | | Professional practise ( internship ) | None | | | | The aim of the course: | | To provide students with the ability to solve a problem, identify and rectify errors, and create the necessary design using the principles of digital design. |
| Learning Outcomes | CTPO | TOA | | Upon successful completion of the course, the students will be able to : | | | | LO - 1 : | Explain the process of analog-to-digital conversion | 1,2,3,4 | 1, | | LO - 2 : | Explain number systems and numerical code types and convert between them | 1,2,3,4 | 1, | | LO - 3 : | Become familiar with the input-output relationships of logic gates and will be able to perform digital circuit simplification by applying Boolean algebra rules. | 1,2,3,4 | 1, | | LO - 4 : | Use Karnaugh maps to simplify digital circuits and perform reduction during the digital circuit simplification process. | 1,2,3,4 | 1, | | LO - 5 : | Implement digital designs using combinational circuits such as encoders, decoders, multiplexers, demultiplexers, comparators, and arithmetic logic circuits. | 1,2,3,4 | 1, | | LO - 6 : | Explain the operation principles of synchronous logic circuits and perform time-dependent input/output analyses for latch (SR and D) and flip-flops (SR, JK, D, T). | 1,2,3,4 | 1, | | LO - 7 : | Draw a suitable state diagram for problems related to synchronous sequential logic circuits, create a state transition table, reduce the state transition table, implement the circuit design with the desired flip-flops, and finally, validate it using simulation software. | 1,2,3,4 | 1, | | LO - 8 : | Design counter circuits using the required flip-flops, simulate their operation and explain the types and principles of operation of registers. | 1,2,3,4 | 1, | | LO - 9 : | Explain the basic principles of programmable logic and can implement simple designs using VHDL | 1,2,3,4 | 1, | | CTPO : Contribution to programme outcomes, TOA :Type of assessment (1: written exam, 2: Oral exam, 3: Homework assignment, 4: Laboratory exercise/exam, 5: Seminar / presentation, 6: Term paper), LO : Learning Outcome | | |
| Digital Systems and Binary Numbers,
Boolean Algebra and Logic Gates,
Logic Circuit Simplification,
Combinatorial Logic and Circuits,
Synchronous and Sequential Logic,
Registers and Counters,
Memory and Programmable Logic (VHDL). |
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| Course Syllabus | | Week | Subject | Related Notes / Files | | Week 1 | Digital Systems and Binary Numbers | | | Week 2 | Digital Systems and Binary Numbers | | | Week 3 | Boolean Algebra and Logic Gates | | | Week 4 | Logic Circuit Simplification | | | Week 5 | Combinatorial Logic and Circuits | | | Week 6 | Combinatorial Logic and Circuits | | | Week 7 | Synchronous and Sequential Logic | | | Week 8 | Synchronous and Sequential Logic | | | Week 9 | Mid-term Exam | | | Week 10 | Synchronous and Sequential Logic | | | Week 11 | Counters | | | Week 12 | Counters | | | Week 13 | Registers | | | Week 14 | VHDL | | | Week 15 | VHDL | | | Week 16 | Final Exam | | | |
| 1 | Harris, S. L., & Harris, D. (2015). Digital design and computer architecture. Morgan Kaufmann | | | 2 | M Morris Mano, M. D. C. (2017). Digital design: with an introduction to the verilog HDL, VHDL, and system Verilog | | | |
| 1 | Prof. Dr. Hüseyin Ekiz, Sayısal Elektronik Ders Notları
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| Method of Assessment | | Type of assessment | Week No | Date | Duration (hours) | Weight (%) | | Mid-term exam | 9 | 28.12.2023 | 2 | 50 | | End-of-term exam | 16 | 17.01.2024 | 2 | 50 | | |
| Student Work Load and its Distribution | | Type of work | Duration (hours pw) | No of weeks / Number of activity | Hours in total per term | | Yüz yüze eğitim | 3 | 14 | 42 | | Sınıf dışı çalışma | 4 | 14 | 56 | | Arasınav için hazırlık | 2 | 7 | 14 | | Arasınav | 2 | 1 | 2 | | Uygulama | 2 | 8 | 16 | | Dönem sonu sınavı için hazırlık | 3 | 5 | 15 | | Dönem sonu sınavı | 2 | 1 | 2 | | Total work load | | | 147 |
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