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FACULTY of ENGINEERING / DEPARTMENT of ELECTRICAL and ELECTRONICS ENGINEERING /
Katalog Ana Sayfa
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ELK3011Circuit Synthesis3+0+0ECTS:4
Year / SemesterFall Semester
Level of CourseFirst Cycle
Status Elective
DepartmentDEPARTMENT of ELECTRICAL and ELECTRONICS ENGINEERING
Prerequisites and co-requisitesNone
Mode of DeliveryFace to face
Contact Hours14 weeks - 3 hours of lectures per week
LecturerProf. Dr. Ayten ATASOY
Co-Lecturer-
Language of instructionTurkish
Professional practise ( internship ) None
 
The aim of the course:
To teach circuit synthesis problems and synthesis methods
 
Learning OutcomesCTPOTOA
Upon successful completion of the course, the students will be able to :
LO - 1 : Describe the circuit synthesis problem2,3,41
LO - 2 : Learn the knowledge on the synthesis of 1-port RC,RL and RLC circuits 1,2,3,41
LO - 3 : Learn the knowledge on the synthesis of 2-port circuits 1,2,31
LO - 4 : Have the knowledge on active and passive synthesis methods1,2,3,41
LO - 5 : Have the knowledge on Butterworth ve Chebyshev type approximations1,2,41
CTPO : Contribution to programme outcomes, TOA :Type of assessment (1: written exam, 2: Oral exam, 3: Homework assignment, 4: Laboratory exercise/exam, 5: Seminar / presentation, 6: Term paper), LO : Learning Outcome

 
Contents of the Course
Network synthesis problem. Synthesis of 1-port passive networks. Positive real functions. Synthesis of LC, RC, RL and RLC networks. Cauer and Foster circuits, Synthesis of passive 2-port networks. Positive real matrices. Synthesis procedures converted to synthesis of 1-port network. Zero shifting technique and its application to RC circuits. Active Circuit Synthesis, Butterworth and Chebyshev approximations.
 
Course Syllabus
 WeekSubjectRelated Notes / Files
 Week 1Network synthesis problem
 Week 2Synthesis of 1-port passive networks, Positive real functions
 Week 3Synthesis of LC networks, Foster circuits
 Week 4Synthesis of LC networks, Cauer circuits
 Week 5Properties of circuit functions for RC, RL circuits.
 Week 6Synthesis of RC, RL and RLC networks
 Week 7Synthesis of passive 2-port networks, Positive real matrices
 Week 8Synthesis procedures converted to synthesis of 1-port network
 Week 9Mid-term exam
 Week 10Zero shifting technique and its application to RC circuits
 Week 11Active Circuit Synthesis
 Week 12Active Circuit Synthesis
 Week 13Butterworth and Chebyshev type approximations
 Week 14Butterworth and Chebyshev type approximations
 Week 15Make up exam
 Week 16End-of-term exam
 
Textbook / Material
1Anday, F., Devre Sentezine Giriş. İTÜ.
 
Recommended Reading
1Gosh Smarajit., Network theory : analysis and synthesis, Prentice-Hall of India.
2Van Valkenburg, M.E., Introduction to Modern Network Synthesis, Wiley.
 
Method of Assessment
Type of assessmentWeek NoDate

Duration (hours)Weight (%)
Mid-term exam 9. Hafta 9. Hafta 2 50
End-of-term exam 15. veya 16. Hafta 15. veya 16. Hafta 2 50
 
Student Work Load and its Distribution
Type of workDuration (hours pw)

No of weeks / Number of activity

Hours in total per term
Yüz yüze eğitim 2 14 28
Sınıf dışı çalışma 2 14 28
Arasınav için hazırlık 3 7 21
Arasınav 2 1 2
Dönem sonu sınavı için hazırlık 4 6 24
Dönem sonu sınavı 2 1 2
Total work load105