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| ELK3011 | Circuit Synthesis | 3+0+0 | ECTS:4 | | Year / Semester | Fall Semester | | Level of Course | First Cycle | | Status | Elective | | Department | DEPARTMENT of ELECTRICAL and ELECTRONICS ENGINEERING | | Prerequisites and co-requisites | None | | Mode of Delivery | Face to face | | Contact Hours | 14 weeks - 3 hours of lectures per week | | Lecturer | Prof. Dr. Ayten ATASOY | | Co-Lecturer | - | | Language of instruction | Turkish | | Professional practise ( internship ) | None | | | | The aim of the course: | | To teach circuit synthesis problems and synthesis methods |
| Learning Outcomes | CTPO | TOA | | Upon successful completion of the course, the students will be able to : | | | | LO - 1 : | Describe the circuit synthesis problem | 1.1 - 1.2 - 1.3 - 2.1 | 1 | | LO - 2 : | Learn the knowledge on the synthesis of 1-port RC,RL and RLC circuits | 1.1 - 1.2 - 1.3 - 2.1 | 1 | | LO - 3 : | Learn the knowledge on the synthesis of 2-port circuits | 1.1 - 1.2 - 1.3 - 2.1 | 1 | | LO - 4 : | Have the knowledge on active and passive synthesis methods | 1.1 - 1.2 - 1.3 - 2.1 | 1 | | LO - 5 : | Have the knowledge on Butterworth ve Chebyshev type approximations | 1.1 - 1.2 - 1.3 - 2.1 | 1 | | CTPO : Contribution to programme outcomes, TOA :Type of assessment (1: written exam, 2: Oral exam, 3: Homework assignment, 4: Laboratory exercise/exam, 5: Seminar / presentation, 6: Term paper), LO : Learning Outcome | | |
| Network synthesis problem. Synthesis of 1-port passive networks. Positive real functions. Synthesis of LC, RC, RL and RLC networks. Cauer and Foster circuits, Synthesis of passive 2-port networks. Positive real matrices. Synthesis procedures converted to synthesis of 1-port network. Zero shifting technique and its application to RC circuits. Active Circuit Synthesis, Butterworth and Chebyshev approximations.
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| Course Syllabus | | Week | Subject | Related Notes / Files | | Week 1 | Network synthesis problem | | | Week 2 | Synthesis of 1-port passive networks, Positive real functions | | | Week 3 | Synthesis of LC networks, Foster circuits | | | Week 4 | Synthesis of LC networks, Cauer circuits | | | Week 5 | Properties of circuit functions for RC, RL circuits. | | | Week 6 | Synthesis of RC, RL and RLC networks
| | | Week 7 | Synthesis of passive 2-port networks, Positive real matrices | | | Week 8 | Synthesis procedures converted to synthesis of 1-port network | | | Week 9 | Mid-term exam | | | Week 10 | Zero shifting technique and its application to RC circuits | | | Week 11 | Active Circuit Synthesis | | | Week 12 | Active Circuit Synthesis | | | Week 13 | Butterworth and Chebyshev type approximations | | | Week 14 | Butterworth and Chebyshev type approximations | | | Week 15 | Make up exam | | | Week 16 | End-of-term exam | | | |
| 1 | Anday, F., Devre Sentezine Giriş. İTÜ. | | | |
| 1 | Gosh Smarajit., Network theory : analysis and synthesis, Prentice-Hall of India. | | | 2 | Van Valkenburg, M.E., Introduction to Modern Network Synthesis, Wiley. | | | |
| Method of Assessment | | Type of assessment | Week No | Date | Duration (hours) | Weight (%) | | Mid-term exam | 9. Hafta | 9. Hafta | 2 | 50 | | End-of-term exam | 15. veya 16. Hafta | 15. veya 16. Hafta | 2 | 50 | | |
| Student Work Load and its Distribution | | Type of work | Duration (hours pw) | No of weeks / Number of activity | Hours in total per term | | Yüz yüze eğitim | 2 | 14 | 28 | | Sınıf dışı çalışma | 2 | 14 | 28 | | Arasınav için hazırlık | 3 | 7 | 21 | | Arasınav | 2 | 1 | 2 | | Dönem sonu sınavı için hazırlık | 4 | 6 | 24 | | Dönem sonu sınavı | 2 | 1 | 2 | | Total work load | | | 105 |
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